3

A delay-locked loop with self-calibration circuit for reducing phase error

Year:
2013
Language:
english
File:
PDF, 3.31 MB
english, 2013
10

Clock buffer with duty cycle corrector

Year:
2011
Language:
english
File:
PDF, 1.04 MB
english, 2011
13

A fast-locking PLL with all-digital locked-aid circuit

Year:
2013
Language:
english
File:
PDF, 1.54 MB
english, 2013
16

Frequency presetting and phase error detection technique for fast-locking phase-locked loop

Year:
2014
Language:
english
File:
PDF, 1.30 MB
english, 2014
23

Pulsewidth control loop with low control voltage ripple

Year:
2013
Language:
english
File:
PDF, 1.04 MB
english, 2013